Leakage assessment has become very crucial part of circuit design, both in portable low-power applications where leakage current can limit the interval between battery recharges, and also high-power applications where the leakage current can be a substantial portion of the total power dissipation of the operating unit. Current look-up table and general-purpose circuit simulation program (e.g., SPICE) model approaches offer limited benefit at best and the scope of coverage is very limited as well. For example, current SPICE models and circuit simulation programs are not generally focused on calculating quiescent current (often called IDDQ).
It would be highly desirable to provide an improved solution for circuit simulators to implement IDDQ leakage-specific models into the current design flows.
Furthermore, it is desirable to provide an improved solution for circuit simulators to implement IDDQ leakage specific models into the current design flows wherein the leakage model covers all geometries with wide temperature and voltage ranges without tedious stacking factor calculations nor spread sheet based IDDQ calculation.
Further more, in such a solution, it is desirable to provide an improved solution for circuit simulators to implement leakage specific models into the current design flows wherein the leakage model allows all parasitic and proximity effects to be incorporated for IDDQ calculation.